Great efforts have been made in radio frequency (RF) design towards one-chip transceivers in standard complementary metal oxide semiconductor (CMOS) in recent years. Particularly the CMOS implementation of frequency dividers and frequency synthesizers—one of the key building blocks in a transceiver—have attracted a lot of attention. The most notable trend here is the zipper divider architecture and the so-called current-mode logic (CML).
The known zipper divider is comprised of a chain of divide-by-⅔ cells of identical circuitry. Shown in FIG. 1 is a conventional divide-by-⅔ cell 10 having five terminals 11-15: clock input (CKin) 11, divided clock output (CKout) 12, mode control input (MDin) 13, mode control output (MDout) 14, and a programming input (P) 15. Each divide-by-⅔ cell 10 consists of two circuit blocks: a prescaler logic block 16 which divides either by 2 or 3, controlled by a swallow signal (SW) generated by another block called end-of-cycle logic 17. When a programming bit P=0 (with MDin=1 or MDin=0) is applied at the programming input 15, then the cell 10 divides by 2 and when P=1 and MDin=1 it divides by 3.
The divide-by-⅔ cells are typically implemented in CML. An elementary CML logic circuit comprises several stacked differential pairs, two resistive or active loads, and one tail current source. Further details concerning CML implemented zipper dividers is described by C. Vaucher and Z. Wang in “A low-power truly-modular 1.8 GHz programmable divider in standard CMOS technology”, ESSCIRC'99. pp.406-409, 1999, and by C. Vaucher, I. Ferencic, M. Locher, S. Sedvallson, U. Voegeli, and Z. Wang in “A family of low-power truly modular programmable dividers in standard 0.35-mm CMOS technology”, SC-35, No. 7, pp.1039-1045, 2000.
An example of a known frequency divider 20 comprising a chain of six divide-by-⅔ cells 21-26 and an input latch 27 is depicted in FIG. 2A. The divider 20 is capable of operating at an input clock frequency (CK1) in the GHz range. FIG. 2B shows the terminal signals of the frequency divider 20. The clock input and clock output signals (CK1-CK7) are depicted in the plots on the left hand side of FIG. 2B and the mode control signals (MD1-MD6) are depicted on the right hand side together with CK1. The amplitudes of the clock input and clock output signals (CK1-CK7) range in the present example between−500 mV and +500 mV (peak-to-peak) since the divider 20 is realized in CML. In the present example, for most of the time, the cells 21-26 divide their respective clock input by 2. If the division ratio is 3, the pulse width is wider, as visible on the left hand side of FIG. 2B. In case of the signal CK3, for example, at the times t1 and t2 the division ratio is 3. This is due to the fact that a binary word P=111111 is applied to the programming inputs (P0-P5) of the input latch 27. If the programming inputs are always logic “1” the division ratio of the individual cells 21-26 is only determined by the mode control signal (MD) issued by a subsequent cell to a preceding cell.
The major effort in the telecommunications IC industries is to constantly improve the quality and to reduce the manufacturing costs. Along with the evolution from the second generation such as GSM to the third generation UMTS, new innovative techniques and technologies are vital in this fiercely competitive market. One of the new techniques is the so-called fractional-N PLL transmitter, where a PLL is employed not only for the generation of carrier frequencies but also for the modulation of the signals to be transmitted. The benefits of this approach include a comparatively spurious free output spectrum with very low levels of phase noise close to the carrier, and considerable reduction of the manufacturing costs.
One of the key components in this PLL transmitter is the frequency divider. The recent trend of its CMOS implementation is to exploit the above-mentioned zipper divider architecture in combination with CML. Two key performance parameters of the divider are power consumption and the output spectrum purity.
For low-power applications, a divider architecture capable of reducing the power consumption by up to 50% has been proposed in the co-pending patent application entitled “IMPROVED FREQUENCY DIVIDER WITH REDUCED POWER CONSUMPTION, APPARATUS BASED THEREON, AND METHOD FOR POWER EFFICIENT FREQUENCY DIVISION”. This co-pending patent application was filed on Dec. 22, 2000 is currently assigned to the assignee of the present patent application. Application number 00128322.5 was assigned.
While the phase noise is used to describe the spectrum purity in the frequency domain, jitter is used as a measure for the same thing in the time domain. Jitter results from circuit noises that change the transition of signals across the threshold. Jitters are present in every cell of the zipper divider 20 of FIG. 2A. Due to the asynchronous nature of this kind of divider 20, jitters accumulate along the signal path from the left to the right of the chain. This effect is called jitter accumulation. If the signal MD4 is taken as the output 28 (cf. FIG. 3), for example, all jitters along the path accumulate toJOUT2=JIN2+JC12+JC22+JC32+JC42+JM42where JIN is the standard deviation of the jitter associated with the input CK1, JCi the standard deviation of the jitter added to its output CK(i+1) by cell i, and JM4 the jitter deviation added to MD4 by the cell 25, as depicted in FIG. 3. Because the current consumption is scaled down in the zipper divider 20 and at the same time the resistive load is scaled up with the frequency cell by cell, jitters added by one cell are larger than those added by its preceding cell.
Jitter is a major concern in frequency dividers, oscillators, frequency synthesizers, etc. because introducing even a small jitter into these circuits leads to dramatic changes in its frequency spectrum and timing properties, thus resulting in lower signal-to-noise ratio, increased bit error rates, and higher interference to neighboring channels. Jitter is also important in clocked and sampled-data systems because the zero-crossing often contain information so any uncertainties in switching instants will cause error.
Until now, the spectrum purity in general and jitter accumulation in particular is not seriously considered when designing zipper divider circuitry in CML.
It is thus an objective of the present invention to improve current divider circuitry.
It is another objective of the present invention to provide a frequency divider with reduced or eliminated jitter.
It is another objective of the present invention to provide a frequency divider with improved spectrum purity.